Estimation of the Cycle Time Distribution of a Wafer Fab by a Simple Simulation Model
نویسنده
چکیده
Semiconductor manufacturing facilities are very complex. To obtain a fundamental understanding of the effects of dispatch and lot release rules on the factory performance based on a full factory model is difficult. In this paper, we therefore present a simple factory model that is intended to show essentially the same behavior as the complete factory. The model consists of the bottleneck workcenter of the full factory model represented in full detail and several delay units for the aggregated remaining machines.
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